ASIC flow, Synthesis, STA, Physical Design - Cadence Genus, Tempus, Innovus tool flow & Synopsys ICC2 tool flow
Sub Category
- Other Design
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Objectives
- ASIC Flow in brief
- Logical Synthesis vs Physical Synthesis
- Timing Concepts, definitions
- Static Timing Analysis (STA)
- Timing paths, Contraints, modes
- Synthesis example execution with Genus tool
- STA example execution with Tempus tool
- Physical design flow using Innovus tool
- Floorplan
- Placement
- Clock Tree Synthesis (CTS)
- Routing
Pre Requisites
- Basics of RTL design using Verilog
- Digital Fundamentals
- Verilog Language
FAQ
- Q. How long do I have access to the course materials?
- A. You can view and review the lecture materials indefinitely, like an on-demand channel.
- Q. Can I take my courses with me wherever I go?
- A. Definitely! If you have an internet connection, courses on Udemy are available on any device at any time. If you don't have an internet connection, some instructors also let their students download course lectures. That's up to the instructor though, so make sure you get on their good side!
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