Learn AXI4 Bus implementation for your next FPGA design in Intel/Altera or AMD/Xilinx
Sub Category
- Programming Languages
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Objectives
- Learn the FPGA based AXI4 Bus Protocol, including AXI4-Lite and AXI4 Stream with RTL / Verification in VHDL and Verilog
- AXI4 Bus signals and Master / Slave Handshaking
- Verification of the AXI4 Protocol and interfacing to Vendor IP
- Simulation Demonstrations in Verilog and VHDL with sample code files
Pre Requisites
- Understand basic FPGA logic design in either VHDL or Verilog. Some experience with behavioral simulators can be helpful.
FAQ
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